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october 2000 1/11 ? 1 VN710SP automotive glow plug driver n cmos compatible input n on state open load detection n off state openload detection n shorted load protection n undervoltage and overvoltage shutdown n protection against loss of ground n very low stand-by current when enable pin is low n reverse battery protection (*) description the VN710SP is a monolithic device made using stmicroelectronics vipower m0-3 technology, intended for driving any kind of load with one side connected to ground. active v cc pin voltage clamp protects the device against low energy spikes (see iso7637 transients compatibility table). active current limitation combined with thermal shutdown protect the device against overload. after a thermal shutdown event, device stays latched off and diagnostic stays at a low level until next falling edge of input signal. the device detects open load condition both in on state and off state. output shorted to v cc is detected in the off state. device automatically turns off in case of ground pin disconnection. enable pin allows to switch the device to idle state with very low quiescent current from v cc . when enable is low, device turns off regardless of input pin state. type r ds(on) i out v cc VN710SP 18m w 35 a 16 v 1 10 powerso-10 ? preliminary data undervoltage overtemperature v cc gnd input output overvoltage current limiter logic driver power clamp status v cc clamp on state openload off state openload and output shorted to v cc detection enable detection detection detection detection block diagram (*) see application schematic at page 7
2/11 VN710SP absolute maximum rating connection diagram (top view) symbol parameter value unit v cc dc supply voltage 41 v -v cc reverse dc supply voltage -0.3 v -i gnd reverse dc ground pin current -200 ma i out dc output current internally limited a -i out reverse dc output current -35 a i in dc input current +/-10 ma i en dc enable current +/-10 ma i stat dc status current +/-10 ma v esd electrostatic discharge (r=1.5k w ; c=100pf) 2000 v p tot power dissipation at t c =25 c89w t j junction operating temperature internally limited c t c case operating temperature -40 to 150 c t stg storage temperature -55 to 150 c 1 current and voltage conventions 1 2 3 4 5 6 7 8 9 10 11 output output output output output ground enable status input n.c. v cc i cc i gnd output v cc gnd status input i out i in i stat v stat v in v cc v out i en v en enable thermal data (*) when mounted on a standard single-sided fr-4 board with 50mm 2 of cu (at least 35 m m thick). symbol parameter value unit r tj-case thermal resistance junction-case 1.4 c/w r tj-amb (*) thermal resistance junction-ambient 52 c/w
3/11 VN710SP electrical characteristics (7vv enh 10 10 2.5 25 20 4 m a m a ma i lgnd output current at turn-off v cc =v gnd =16v v in =v en =n.c.; v out =0v 2ma i l(off1) off state output current v out =0v; v in >v ih 050 m a i l(off2) off state output current v out =3.5v; v in >v ih ; v en >v enh -75 0 m a symbol parameter test conditions min typ max unit t d(on) turn-on delay time r l =0.85 w , from v in falling edge to v out =1.3v 40 m s t d(off) turn-off delay time r l =0.85 w , from v in rising edge to v out =11.7v 80 m s dv out / dt (on) turn-on voltage slope r l =0.85 w , from v out =1.3v to v out =10.4v 0.1 v/ m s dv out / dt (off) turn-off voltage slope r l =0.85 w , from v out =11.7v to v out =1.3v 0.1 v/ m s symbol parameter test conditions min typ max unit v il input low level 1.25 v i il low level input current v in =1.25v; v en >v enh -35 m a v ih input high level 3.25 v i ih high level input current v in =3.25v; v en >v enh v in =3.25v; v en =0v -300 -4 -4 m a m a v i(hyst) input hysteresis voltage 0.5 v v icl input clamp voltage i in =1ma i in =-1ma 66.8 -0.7 8v v symbol parameter test conditions min typ max unit v enl enable low level 1.25 v i enl low level enable current v en =1.25v 4 m a v enh enable high level 3.25 v i enh high level enable current v en =3.25v 35 m a v ehyst enable hysteresis voltage 0.5 v v encl enable clamp voltage i en =1ma i en =-1ma 66.8 -0.7 8v v 1
4/11 VN710SP electrical characteristics (continued) status pin (open drain) protections openload detection symbol parameter test conditions min typ max unit v stat status low output voltage i stat =1.6ma 0.5 v i lstat status leakage current normal operation; v stat =5v 10 m a c stat status pin input capacitance normal operation; v stat =5v 100 pf v scl status clamp voltage i stat =1ma i stat =-1ma 66.8 -0.7 8v v symbol parameter test conditions min typ max unit t tsd shut-down temperature 170 190 c t r reset temperature 135 c t hyst thermal hysteresis 7 15 c t sdl overload detection delay t j >t tsd 20 m s i lim current limitation 35 55 80 a v demag turn-off output clamp voltage i out =2a; v in =5v; l=6mh v cc -41 v cc -48 v cc -55 v symbol parameter test conditions min typ max unit i ol openload on state detection threshold v in =0v 0.1 1 2 a v ol openload off state voltage detection threshold v in =5v 1.5 2.5 3.5 v t dol(off) openload detection delay at turn-off 500 m s t dol(on) openload detection delay at turn-on i out =0v 200 m s v in v stat t dol(off) openload status timing (with external pull-up) v in v stat overtemp status timing t sdl i out v ol t dol(on) t j >t tsd 2
5/11 VN710SP truth table (*) latched on first overtemperature event; latch cleared on next input falling edge. conditions enable input output status normal operation h h h l l h h h current limitation h h h l l x h h overtemperature h h l h l (*) l l (*) l undervoltage h h h l l l x x overvoltage h h h l l l h h output voltage > v ol h h h l h h l h output current < i ol h h h l l h h l any l x l h t v out 90% 10% dv out /dt (off) dv out /dt (on ) switching time waveforms 80% t v in t d(on) t d(off)
6/11 VN710SP iso t/r 7637/1 test pulse test levels i ii iii iv delays and impedance 1 -25v -50v -75v -100v 2ms, 10 w 2 +25v +50v +75v +100v 0.2ms, 10 w 3a -25v -50v -100v -150v 0.1ms, 50 w 3b +25v +50v +75v +100v 0.1ms, 50 w 4 -4v -5v -6v -7v 100ms, 0.01 w 5 +26.5v +46.5v +66.5v +86.5v 400ms, 2 w iso t/r 7637/1 test pulse test levels result iiiiiiiv 1 c c c c 2cccc 3acccc 3bcccc 4cccc 5ceee class contents c all functions of the device are performed as designed after exposure to disturbance. e one or more functions of the device is not performed as designed after exposure and cannot be returned to proper operation without replacing the device. electrical transients requirements on v cc pin suggested scheme for iso test pulse output v cc gnd status input enable open from test generator 10k w 10k w 10k w warning: input, enable, status pulled to v cc voltage during negative transient.
7/11 VN710SP gnd protection network against reverse battery solution 1: resistor in the ground line (r gnd only). this can be used with any type of load. the following is an indication on how to dimension the r gnd resistor. 1) r gnd 600mv / (i s(on)max ). 2) r gnd 3 (- v cc ) / (-i gnd ) where -i gnd is the dc reverse ground pin current and can be found in the absolute maximum rating section of the of the devices datasheet. power dissipation in r gnd (when v cc <0: during reverse battery situations) is: p d = (-v cc ) 2 /r gnd this resistor can be shared amongst several different hsd. please note that the value of this resistor should be calculated with formula (1) where i s(on)max becomes the sum of the maximum on-state currents of the different devices. please note that if the microprocessor ground is not common with the device ground then the r gnd will produce a shift (i s(on)max * r gnd ) in the input thresholds and the status output values. this shift will vary depending on many devices are on in the case of several high side drivers sharing the same r gnd . if the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the st suggest to utilize solution 2 (see below). solution 2: a diode (d gnd ) in the ground line. a resistor (r gnd =1k w) should be inserted in parallel to d gnd if the device will be driving an inductive load. this small signal diode can be safely shared amongst several different hsd. also in this case, the presence of the ground network will produce a shift ( j 600mv) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. this shift will not vary if more than one hsd shares the same diode/resistor network. load dump protection d ld is necessary (transil or mov) if the load dump peak voltage exceeds v cc max dc rating. the same applies if the device will be subject to transients on the v cc line that are greater than the ones shown in the iso t/r 7637/1 table. m c i/os protection: if a ground protection network is used and negative transient are present on the v cc line, the control pins will be pulled negative. st suggests to insert a resistor (r prot ) in line to prevent the m c i/os pins to latch-up. the value of these resistors is a compromise between the leakage current of m c and the current required by the hsd i/os (input levels compatibility) with the latch-up limit of m c i/os. -v ccpeak /i latchup r prot (v oh m c -v ih -v gnd ) / i ihmax calculation example: for v ccpeak = - 100v and i latchup 3 20ma; v oh m c 3 4.5v 5k w r prot 18.57k w . recommended r prot value is10k w. 1 application schematic v cc gnd output d gnd r gnd d ld m c +5v r prot v gnd status input +5v r prot r prot enable
8/11 VN710SP openload status input normal operation undervoltage v cc v usd v usdhyst input overvoltage v cc v cc v ov v ov
9/11 VN710SP 1 1 1 dim. mm. inch min. typ max. min. typ. max. a 3.35 3.65 0.132 0.144 a (*) 3.4 3.6 0.134 0.142 a1 0.00 0.10 0.000 0.004 b 0.40 0.60 0.016 0.024 b (*) 0.37 0.53 0.014 0.021 c 0.35 0.55 0.013 0.022 c (*) 0.23 0.32 0.009 0.0126 d 9.40 9.60 0.370 0.378 d1 7.40 7.60 0.291 0.300 e 9.30 9.50 0.366 0.374 e2 7.20 7.60 0.283 300 e2 (*) 7.30 7.50 0.287 0.295 e4 5.90 6.10 0.232 0.240 e4 (*) 5.90 6.30 0.232 0.248 e 1.27 0.050 f 1.25 1.35 0.049 0.053 f (*) 1.20 1.40 0.047 0.055 h 13.80 14.40 0.543 0.567 h (*) 13.85 14.35 0.545 0.565 h 0.50 0.002 l 1.20 1.80 0.047 0.070 l (*) 0.80 1.10 0.031 0.043 a 0o 8o 0o 8o a (*) 2o 8o 2o 8o 1 1 powerso-10 ? mechanical data (*) muar only poa p013p detail "a" plane seating a l a1 f a1 h a d d1 = = = = e4 0.10 a e c a b b detail "a" seating plane e2 10 1 eb he 0.25 p095a
10/11 VN710SP 1 powerso-10 ? suggested pad layout 1 tape and reel shipment (suffix 13tr) reel dimensions all dimensions are in mm. base q.ty 600 bulk q.ty 600 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (+ 2 / -0) 24.4 n (min) 60 t (max) 30.4 tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb 1986 all dimensions are in mm. tape width w 24 tape hole spacing p0 ( 0.1) 4 component spacing p 24 hole diameter d ( 0.1/-0) 1.5 hole diameter d1 (min) 1.5 hole position f ( 0.05) 11.5 compartment depth k (max) 6.5 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed 6.30 10.8 - 11 14.6 - 14.9 9.5 1 2 3 4 5 1.27 0.67 - 0.73 0. 54 - 0.6 10 9 8 7 6 b a c all dimensions are in mm. base q.ty bulk q.ty tube length ( 0.5) a b c ( 0.1) casablanca 50 1000 532 10.4 16.4 0.8 muar 50 1000 532 4.9 17.2 0.8 tube shipment (no suffix) c a b muar casablanca
11/11 VN710SP information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this p ublication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a registered trademark of stmicroelectronics ? 2000 stmicroelectronics - printed in italy- all rights reserved. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com

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